VLSI Design

Recommended Books

  1. Neil Weste, David Harris, CMOS VLSI Design, 4th ed. 2010, Pearson Education, Inc.

Course Learning Outcome


To identify the Physical Layout  and Gate Level System Design using 65 nm ASIC technology.


To discuss a scalar RISC core and Application-Specific Hardware Accelerators. Design and program Uni-core System on Chip (SoC) and Multi-core (SoC) architectures. Bus System Performance (data rate), Processor Performance (FLOPS), Memory Read Write Time.

CLO 3 To use an FPGA logic block for gate and switch level systems.


To develop a layout of semi custom ASIC logic cell of three input lookup table (LUT), an FPGA Configurable Logic Block (CLB) by using VLSI Digital Schematic Editor & Simulator.

CLO -PLO Mapping

Course Code CLOs/ PLOs PLO1 PLO2 PLO3 PLO4 PLO5 PLO6 PLO7 PLO8 PLO9 PLO 10 PLO 11 PLO 12
BS-122 CLO1   X                      
CLO2     X                    
CLO3     X                  
CLO4          X              

Program Learning Outcomes

PLO1: Engineering Knowledge

PLO2: Problem Analysis 

PLO3: Design/Development of Solutions

PLO4: Investigation

PLO5: Modern Tool Usage 

PLO6: The Engineer and Society

PLO7: Environment and Sustainability

PLO8: Ethics

PLO9: Individual and Team Work

PLO10: Communication

PLO11: Project Management

PLO12: Lifelong Learning